A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell

S O Frake,Michael Knecht,Philip J Cacharelis,Michael W Hart,Martin H Manley, Robert E Zeman, Rick Ramus

New York, NY, USA（1989）

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摘要

The authors describe a 9-ns CMOS programmable logic device (PLD) with a standby current of 10 mu A. The circuit is a 24-pin PLD with 10 I/Os (input/outputs) and 12 dedicated inputs. Each I/O has eight summed-product terms and an output-enable control product term feeding into a programmable macrocell. Most standard 24-pin PLDs can be emulated by selectively programming the macrocell architecture bits. Bit-line precharging circuitry is used to reduce the speed degradation caused by designing for low standby current. 'Ground bounce' is alleviated by controlling the output buffer speed. The circuit has been fabricated in a 1- mu m single-polysilicon CMOS EPROM (electrically programmable read-only memory) technology that has been optimized for speed rather than for packing density. Device and technology characteristics are summarized.<>

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关键词

cmos integrated circuits,prom,integrated circuit technology,logic arrays,1 micron,10 mua,9 ns,cmos,pld,characteristics,electrically programmable read-only memory,ground bounce,low standby power,optimized for speed,polycrystalline si,precharging circuitry,programmable logic device,programmable macrocell,single-poly eprom cell,single-polysilicon cmos eprom,standby current,read only memory,input output

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