CM_ISA++: an Instruction Set for Dynamic Task Scheduling Units for More Than 1000 Cores
2014 27th IEEE International System-on-Chip Conference (SOCC)（2014）
关键词
instruction sets,processor scheduling,reduced instruction set computing,CM_ISA++,CoreManager implementation,RISC-based implementation,RISC-based scheduling,application-specific instruction set,data transfer,dynamic scheduling,dynamic task scheduling unit,high task throughput,many-core systems,on-chip memory,processing element allocation performance,processing elements,superior scheduling performance,system scalability
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