Re-visit blocking texture cache design for modern GPU
SoC Design Conference（2014）
摘要
Texture cache plays a significant position in GPU design especially in a limited memory bandwidth environment such as mobile SoC system. In this paper, we evaluate the 6D blocking texture cache design through a sophisticated GPU simulator using DRAM memory model. Our experiment reveals that using a larger block can take advantage of the spatial locality of texel accesses, however, fetching a larger block which requires several burst runs in DRAM access, results in poor memory access efficiency. As a result, the block size used has to match with the DRAM burst length for the best memory access efficiency.
更多查看译文
关键词
dram chips,cache storage,graphics processing units,6d blocking texture cache design,dram access,dram memory model,gpu simulator,poor memory access efficiency,texel accesses,dram model,gpu architecture,texture cache,memory management,data models,instruction sets
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要