ESD characterization and design guidelines for interconnects in 28nm CMOS

Zongyu Dong,Fei Lu,Li Wang,Rui Ma,Chen Zhang,Hui Zhao,Aiping Wang,Shijie Wen,Rita Wong,Rita Fung, Chris Chu,J C Watt,Agha Jahanzeb,P K Liaw

Interconnect Technology Conference / Advanced Metallization Conference（2014）

引用 5|浏览50

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摘要

This paper reports comprehensive transient electrostatic discharge (ESD) characterization of backend interconnects in a foundry 28nm CMOS. Testing results reveal details on metal current handling capability and on-chip ESD protection ability. ESD design guidelines for interconnects are provided for chip-level ESD protection circuit designs in 28nm CMOS.

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关键词

cmos integrated circuits,electrostatic discharge,integrated circuit interconnections,cmos,esd characterization,esd design,backend interconnects,chip-level esd protection circuit designs,electrostatic discharge characterization,metal current handling capability,on-chip esd protection,size 28 nm,silicon,metals

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