Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

Jun-Kai Zhao,Yi-Wei Chiu,Shyh-Jye Jou,Yuan-Hua Chu

SoC Design Conference（2014）

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摘要

In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

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关键词

sram chips,logic design,macros,power aware computing,pc-dvs scheme,sram macro design,frequency 500 khz,leakage power consumption,low-voltage regime,pulse-controlled dynamic voltage scaling scheme,sub-banks,variation immunity,voltage 0.35 v,voltage 0.5 v,cmos integrated circuits,cmos technology

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