Design of a wideband digitally controlled oscillator
Solid-State and Integrated Circuit Technology(2014)
摘要
This paper presents a wide-band digitally controlled oscillator (DCO) applied in all digital phase locked loop (ADPLL) of which the tuning range is 3GHz-5.3GHz. Capacitor tank of the oscillator contains 3 major arrays: coarse tuning bank, medium tuning bank and fine tuning bank (including fractional tuning capacitors), which are all formed by varactors. Post-layout simulation is done to verify its performance on SMIC 40nm process. The oscillator phase noise is -137dBc/Hz at 3MHz, 3.7GHz, and power consumption is 8.6mW and 7mW respectively where center frequency is 3GHz and 5.3GHz.
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关键词
cmos digital integrated circuits,digital circuits,field effect mmic,microwave oscillators,phase locked loops,smic process,all digital phase locked loop,coarse tuning bank,fine tuning bank,fractional tuning capacitors,frequency 3 ghz to 5.3 ghz,medium tuning bank,post layout simulation,size 40 nm,wideband digitally controlled oscillator
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