CDM protection of a 3D TSV memory IC with a 100 GB/s wide I/O data bus

Makoto Nagata,Satoshi Takaya,Hiroaki Ikeda,D Linten,Mirko Scholz,Shihhung Chen,Keiichi Hasegawa,Taizo Shintani,Masanori Sawada

Electrical Overstress/Electrostatic Discharge Symposium（2014）

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摘要

For the first time, CDM stress tests are studied on a 3D TSV stacked IC for memory applications. The stacked dies have each their ESD protection, but no dedicated ESD protection was placed on the TSVs. A CDM protection level of more than 1.5 kV is obtained.

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关键词

electrostatic discharge,integrated circuit testing,storage management chips,three-dimensional integrated circuits,3d tsv memory ic,3d tsv stacked ic,cdm protection,cdm stress tests,esd protection,bit rate 100 gbit/s,stacked dies,wide i/o data bus,stress

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