Nfet FDSOI Activated by Low Temperature Solid Phase Epitaxial Regrowth: Optimization Guidelines
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)（2014）
Key words
cryogenic electronics,field effect transistors,silicon-on-insulator,solid phase epitaxial growth,3D sequential integration,KMC process simulation,LDD implantation,LT activation,SPER,electrical data,first spacer,fully depleted silicon on insulator,highly doped abrupt junctions,low temperature device performance,low temperature solid phase epitaxial regrowth,nFET FDSOI,optimization guidelines,raised source drain epitaxy,standard planar technology
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