Single-Bit Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters

The oversampling requirement in a delta–sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, high-speed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three.