Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS

Luke Wang,Qiwei Wang,Anthony Chan Carusone

PROCEEDINGS OF THE 40TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE (ESSCIRC 2014)（2014）

引用 13|浏览13

关键词

CMOS integrated circuits,analogue-digital conversion,calibration,digital-analogue conversion,sample and hold circuits,CMOS,analog-to-digital converter,background timing skew calibration method,capacitive C-2C DAC,front-end track and hold samplers,power 138.6 mW,power 34.2 mW,size 65 nm,successive approximation register,time interleaved C-2C SAR ADC,two-level hierarchical interleaving,voltage 1 V,word length 8 bit

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