A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy

Kun Ao,Yajuan He, Liang Li,Yuxin Wang,Qiang Li

ISIC（2014）

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摘要

A 14-b 100-MS/s pipeline analog-to-digital converter (ADC) is presented. The ADC uses six 4-b stages with 2-b interstage redundancy to relax the requirements of Sub-ADC nonlinearity and interstage offset. The ADC, implemented in a 0.18-μm CMOS process, achieves 70.3-dB signal-to-noise and distortion ratio (SNDR), 83.7-dB spurious free dynamic range (SFDR) and 11.3 effective number of bit (ENOB) with 30-MHz input at full 100-MHz sampling rate. The ADC dissipates 342mW from 3.3-V supply.

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关键词

cmos integrated circuits,analogue-digital conversion,2b interstage redundancy,cmos process,analog-to-digital converter,frequency 100 mhz,frequency 30 mhz,interstage offset,pipelined a/d converter,power 342 mw,size 0.18 mum,subadc nonlinearity,voltage 3.3 v,pipelines,redundancy,capacitors

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