8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS

Jan R Westra,Jan Mulder,Yi Ke,Davide Vecchi,Xiaodong Liu,Erol Arslan,Jiansong Wan,Qiongna Zhang,Sijia Wang,Frank M L Van Der Goes,Klaas Bult

Solid-State Circuits Conference Digest of Technical Papers（2014）

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摘要

The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. For the implementation of high-density 10GBASE-T network switches, highly integrated transceivers are required that have both a small form factor and high power efficiency. This paper describes an analog front-end (AFE) that is used in a quad-port 10GBASE-T transceiver chip. The small form factor of the AFE allows for the use of a 23×23mm2 BGA package, enabling implementation of 48-port switches with all transceivers in a single row on the PCB pitch-matched to the RJ45 connector arrays. The design achieves >62dBc transmitter SFDR, >62dBc echo cancellation (EC) SFDR, and >60dBc receiver SFDR up to 400MHz. It occupies an area of 15.1mm2 per port in a 40nm CMOS process. At 100m full 10Gb/s traffic, the AFE dissipates less than 1.75W.

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关键词

cmos integrated circuits,ieee standards,ball grid arrays,echo suppression,electric connectors,local area networks,low-power electronics,printed circuits,semiconductor switches,transceivers,twisted pair cables,10gbase-t network switches,afe,bga package,cmos process,ec sfdr,ieee802.3an 10gbase-t standard,pcb pitch-matched,rj45 connector arrays,utp cable,analog front-end,bit rate 10 gbit/s,echo cancellation sfdr,form factor,full-duplex 10gbase-t transceiver,full-duplex ethernet transmission,high power efficiency,integrated transceivers,power 1.75 w,quad-port 10gbase-t transceiver chip,size 100 m,size 40 nm,low power electronics

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