Lookup-table-based background linearization for VCO-based ADCs

Custom Integrated Circuits Conference(2014)

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摘要
A lookup-table digital correction technique enabled by the “Split ADC” calibration approach is described for linearization of VCO-based ADCs. Measured results for a prototype design with 10b resolution in a 180nm CMOS process show ENOB improved to 9.41b from an uncorrected 3.5b. The background LMS calibration procedure is tolerant of different input signals and corrects linearity over the entire range covered by the input signal excursion. An input dither of 3% of the ADC reference allows absolute accuracy in scale factor calibration.
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关键词
CMOS integrated circuits,analogue-digital conversion,calibration,integrated circuit design,least mean squares methods,linearisation techniques,table lookup,voltage-controlled oscillators,CMOS process,VCO based ADC,background LMS calibration procedure,lookup table based background linearization,lookup table digital correction technique,size 180 nm,split ADC calibration
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