Author retrospective for design tradeoffs for tiled CMP on-chip networks.

ABSTRACTIn the eight years that have passed since we published "Design Tradeoffs for Tiled CMP On-Chip Networks," on-chip interconnection networks have become pervasive, as semiconductor scaling has allowed increasing numbers of processor cores and components to be integrated on a chip. The contributions of the paper, in particular the detailed technology models and the use of channel slicing and concentration to improve efficiency, remain as valid today as they were when we began the research that led to the paper. The network-on-chip (NoC) design methodology presented in the paper is widely used today. In this retrospective, we review the more significant contributions of the original paper, and comment on the impact it had on subsequent research.