Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem
ICASSP(2014)
摘要
It is impractical to apply a general spike sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable spike sorting hardware with large number of input channels. In this paper, we provide a 128-channel spike detection processor for spike sorting microsystem without compromise of the power efficiency. This chip consumes only 87.02uW and 9.7uW/mm2 of power density, fabricated with 90nm low-leakage CMOS process.
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关键词
cmos integrated circuits,low-leakage cmos process,power consumption,microprocessor chips,power efficiency,spike detection,power density,neural activity,low power spike detection processor design,low-power electronics,general spike sorting algorithm,vlsi,integrated circuit design,size 90 nm,128-channel spike sorting microsystem,neural signal processing,programmable spike sorting hardware,brain signal characteristics,spike sorting,input electrodes,chip area,vlsi architecture design,neural chips,sorting,low power electronics
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