Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA

    FPGA, pp. 240-249, 2015.

    Cited by: 41|Bibtex|Views19|Links
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    Keywords:
    clos networkfpga accelerationmemory efficiencygeneralsortingMore(2+)

    Abstract:

    Parallel sorting networks are widely employed in hardware implementations for sorting due to their high data parallelism and low control overhead. In this paper, we propose an energy and memory efficient mapping methodology for implementing bitonic sorting network on FPGA. Using this methodology, the proposed sorting architecture can be b...More

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