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Floating-Point DSP Block Architecture for FPGAs

FPGA, pp.117-125, (2015)

Cited by: 59|Views124
EI

Abstract

This work describes the architecture of a new FPGA DSP block supporting both fixed and floating point arithmetic. Each DSP block can be configured to provide one single precision IEEE-754 floating multiplier and one IEEE-754 floating point adder, or when configured in fixed point mode, the block is completely backwards compatible with cur...More

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