Physical Design Challenges in the Chip Power Distribution Network.

ABSTRACTThe power supply and ground networks in large integrated circuits or, simply, the power grids, have become very large billion-node metal interconnect structures that often span all levels of the metal stack. The grid may be connected to about 2,000 C4 pads at the top layers and to hundreds of millions of gates and other circuitry at the bottom. It is not uncommon to reserve the top metal layers exclusively for the power grid. However, the extensive use of metal resources on lower metal layers for the grid has become a real bottleneck for signal routing. This adds time and cost to the overall chip design project and represents a problem for physical design. Yet there are reasons to believe that allocation of so much metal resources to the grid is ``overkill'' and that there is much room for improvement. The grid is over-designed because of lack of certainty about its safety from various concerns, like electromigration, IR drop, and inductive drop. There are also open problems in the grid design problem itself, which may be viewed as an optimization problem, albeit a very difficult one. In this talk, I will review developments in the verification of power grids that aim to provide certainty that the grid is safe, and indicate directions for possible ways that the grid may be automatically generated to suit various objectives.