A general scheme for noise-tolerant logic design based on probabilistic and DCVS approaches

The performance of logic function could be affected significantly by the noise effect as the dimension of CMOS devices scales to nanometers. Thus, many pertinent researches about noise-tolerant logic gate have received growing attention. Considering the randomness as the noise's nature, probabilistic-based approach proves better noise-immunity and three design schemes with the technique of Markov Random Field (MRF) have been proposed in [1]-[3]. In this paper, a general circuit scheme for noise-tolerant logic design based on MRF theory and Differential Cascode Voltage Switch (DCVS) technique has been proposed, which is an extension of the work in [3], [4]. A DCVS block with only four transistors has been successfully inserted to the original circuit scheme from [3] and extensive simulation results based on HSPICE show that our proposed design can operate correctly with the input signal of 1dB SNR. When using the Kullback-Leibler Distance (KLD) [5] as the evaluation parameter, the KLD value of our design decreases by 76.5% on average than [3] which means that superior noise-immunity could be obtained through our work.