Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.

•Our RAP model enables systematic CMOS fault abstraction and error propagation.•RAP assumes that physically induced faults eventually manifest as bit flips.•Higher layer error models can be derived from probabilistic bit flip functions.•SoC designers can optimize system resilience across multiple abstraction levels.•Real-world case studies with SRAM soft-errors in CPU cache and MIMO detector are shown.