4×, 3-level, blind ADC-based receiver

Natasa Kovacevic,Mohammad Sadegh Jalali,Jenwei Liang,C Ting,Ali Sheikholeslami,Masaya Kibune,Hirotaka Tamura

Electronics Letters （2015）

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摘要

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <;10-12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UIpp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.

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关键词

cmos digital integrated circuits,analogue-digital conversion,clock and data recovery circuits,decision feedback equalisers,receivers,4× 3-level blind adc-based receiver,ber,cdr design,cmos technology,dfe,fr4 channel,analogue-to-digital converter,bit error rate,bit rate 5 gbit/s,digital clock and data recovery design,high-frequency jitter tolerance,power 63 mw,power 86 mw,power consumption,size 65 nm,speculative decision-feedback equaliser

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