MACS: A Highly Customizable Low-latency Communication Architecture

Networks-on-chips (NoCs) are an increasingly popular communication infrastructure in single chip VLSI design for enhancing parallelism and system scalability. Processing elements (PEs) connect to a communication topology via NoC switches, which are responsible for runtime establishment and management of inter-PE communication channels. Since NoC switch design directly affects overall system performance and exploited communication parallelism, much previous work focused on efficient NoC switch design. In this paper, we present MACS-a highly parametric NoC switch architecture that provides reduced data transfer latency, increased designer flexibility, and scalability as compared to previous architectures by combining and enhancing several NoC design strategies. MACS enhances inter-PE communication using a circuit switching technique with minimal adaptive routing and a simple and fair path resolution algorithm to maximize bandwidth utilization. We evaluate area and performance of an FPGA implementation of MACS, and, show that compared to previous work, MACS offers a 2x to 7x decrease in average channel setup latency, a 1.7x to 2x reduction in area requirements, similar average packet latency, up to a 6x increase in the network saturation point, and up to a 1.4x increase in bandwidth utilization. Additionally, we illustrate MACS's low average channel setup latency using six network traffic patterns and eight parallel JPEG decompression core trace simulations.