Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics

VLSI) Systems, IEEE Transactions  , Volume PP, Issue 99, 2015, Pages 1

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array test-structuresram characterizationmodel-fittingprocess monitortest-time reduction.More(3+)

Abstract:

An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor's characteristics. ...More

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