Area And Energy Efficient 802.11ad Ldpc Decoding Processor

The design of multi-Gbit/s low-density parity-check code (LDPC) decoders has become a hot topic in recent years to meet the growing demand of the transformation towards 4G. An area and energy efficient multi-Gbit/s LDPC decoder engine with a fully paralleled layered architecture based on an application-specific instruction set processor (ASIP) using Synopsys IP designer is presented. When the ASIP core is instantiated for 802.11ad, it achieved a throughput of up to 7 Gbit/s at three iterations with a latency of 95 ns, a record energy efficiency of 2.5 pJ/bit/iteration and an area efficiency of 54.5 Gbit/s/sq-m in CMOS 28 nm technology for the 1/2 rate, showing it to be competitive against published ASIC solutions.