3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

ISSCC(2015)

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摘要
Emerging standards in wireline communication are defining a path to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that supports both NRZ and PAM4 modulations and operates from 16 to 40Gb/s. The TX incorporates a 4-tap NRZ FIR filter that is reconfigurable to drive PAM4 levels, quarter-rate clocking with a high-bandwidth 4:1 serializer, a duty-cycle and quadrature-error correction circuit with statistical phase error detection, and compact, multi-layer T-coils for pad capacitance (Cpad) reduction.
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关键词
nrz signaling,cmos integrated circuits,high-speed serdes building blocks,pam4 dual-mode transmitter,radio transmitters,power consumption,cmos process technology,error detection,signal integrity constraints,wireline communication,statistical phase error detection,nrz fir filter,fir filters,quarter-rate nrz,size 14 nm,cmos integrated circuit,quadrature error correction,error correction,transmitters,resistors,modulation
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