Synthesis of TSV Fault-Tolerant 3-D Clock Trees
IEEE Trans. on CAD of Integrated Circuits and Systems(2015)
摘要
In through-silicon-via (TSV) based 3-D integrated chips (ICs), synthesizing 3-D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, flip-flops) through TSVs, any fault on a TSV in the clock tree may cause a chip failure. Therefore, ensuring the reliability of clock TSVs in 3-D ICs is highly important. To cope with clock TSV reliability problem effectively, we propose a new circuit cell called slew-controlled TSV fault-tolerant unit (SC-TFU) which overcomes the limited capability of the conventional TFUs and propose a full solution to the problem of designing and synthesizing 3-D TSV fault-tolerant clock tree based on SC-TFUs. Precisely, for a presynthesized 3-D clock tree, we solve the problem in three steps: 1) performing a comprehensive TSV pairing algorithm to maximally allocate SC-TFUs; 2) replacing TSV pairs obtained in step 1 with SC-TFUs followed by TSV tripling to maximize TSV fault-tolerance under wire and time constraints; and 3) performing a global clock skew tuning process on the SC-TFU embedded 3-D clock tree produced in step 2. Through out experiments, two outstanding benefits are confirmed: 1) our synthesis using SC-TFUs enables a large number of clock TSVs to be paired or tripled to ensure a very high degree of TSV fault-tolerance and 2) our synthesis flow effectively performs tuning of global clock skew whose variation is caused by the inclusion of TSV fault-tolerant cells into 3-D clock trees.
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关键词
through-silicon-via (TSV),slew-controlled tsv fault-tolerant unit,SC-TFU,3D ICs,global clock skew tuning process,TSV,TSV based 3D integrated chips,integrated circuit reliability,tsv fault-tolerance,sc-tfu,tsv based 3d integrated chips,slew-controlled TSV fault-tolerant unit,trees (mathematics),3-D integrated chips (ICs),fault-tolerant,synthesis,3-d integrated chips (ics),three-dimensional integrated circuits,clock tsv reliability,3d clock tree,clock signal,3d ics,clock TSV reliability,fault tolerance,tsv,comprehensive TSV pairing algorithm,clocks,tsv fault-tolerant cells,3D TSV fault-tolerant clock tree,3D clock tree,TSV tripling,integrated circuit design,clock slew,TSV fault-tolerance,3d tsv fault-tolerant clock tree,TSV fault-tolerant cells,tsv tripling,through-silicon-via (tsv),clock skew,through-silicon-via based 3D integrated chips,through-silicon-via based 3d integrated chips,clock sinks,chip failure,comprehensive tsv pairing algorithm
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