Si cap passivation for Ge nMOS applications

Si cap passivation on Ge shows low border trap response.The Si cap passivation is also suitable for Ge nMOS applications.Low Dit at Ec can be achieved by tuning the amount of Si at the interface.A dry O3 process can be used to control the amount of Si that is oxidized. One route to passivate the Ge/high- interface is by depositing an epitaxial Si layer on the Ge surface. Subsequently, the Si layer is partially oxidized and a high- layer is deposited on top. This passivation scheme has proven its efficiency over the last decade for pMOS applications. However, in this paper we demonstrate that this route can also be used for nMOS applications depending on the amount of Si left after the oxidation process. Moreover, the amount of border traps extracted from low frequency capacitance-voltage measurements is low, in contrast to what has been reported on GeO2 passivation. GeO2 passivation results in very low Dit levels at the conduction band edge. Therefore, GeO2 has been put forward as a good candidate for nMOS but it suffers from border traps in the oxide. Si cap passivation can solve both problems: Dit at the interface as well as the border traps in the oxide.