A novel structure of FPGA-based Viterbi decoder

There are two kinds of implementations of the Viterbi decoder, i.e., software- based and hardware-based. A FPGA-based hardware implementation of Viterbi decoder is presented in this paper. The proposed design of Viterbi decoder considers the optimization of the whole system including calculation process, storage form and structure design, which is taken LUT form to get the branch metric value quickly and the pipeline trace back to operate survivor path storage. The Viterbi decoder is designed and implemented on the platform QuartusII 8.1 which carries out the decoding of convolution codes correctly. The experimental results show that the FPGA resource consumption is reduced, the system operating speed is improved and the whole system power consumption is reduced as well. © 2011 ISSN.