A Lvds Transmitter With Low-Jitter Pll And Pre-Emphasis For Serial Link

A high-speed low-voltage differential signal (LVDS) transmitter adopts an improved feedback structure to stabilize the output current and the common-mode voltage of the differential szgnal. Meanwhile, a conventional VCO and pre-emphasis circuit is improved to reduce jitter and inter-symbol interference in the transmission line. The transmitter is implemented in 0,130m standard 1P8M CMOS process and integrated into a high speed SERDES (Serial and De-serial) chip. The test results of the SERDES show that the differential swing voltage and common-mode voltage of LVDS are 450mv and 1,2V, respectively. The pre-emphasis compensates enough channel loss at 1,5 Gb/s. The total power consumption of the transmitter is 80mW at 1,5Gb/s,