CMOS compatible MEMs process for post interconnect single chip integration application

ASICON(2011)

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摘要
In this work, CMOS compatible MEMs platform process was developed on 200mm Cu BEOL Line. The fabrication technology was dedicated to micro-bridge structure based MEMs application. The integration scheme was post interconnect single chip integration, in which MEMs was built directly on standard CMOS interconnect structure and can share Si area with standard CMOS circuit. Because of the shared Si area and single chip integration scheme, the application cost can be greatly reduced with increasing performance. Modified CMOS-BEOL process was used to develop the CMOS-MEMs interface structure, and top metal was used both as the functional layer and PAD layer with lower step height by optimized planarization process. As to the bridge structure, TaN was used as electrode material, and alpha-Si film was used as the sacrificial material fabricated by low Temperature PECVD technology. No metal or dielectric material plug was used for the anchor supporting structure, which make the process much more controllable and flexible. For one of the Sensor product application, the sensing material was using B-doped alpha-Si film fabricated by PECVD and in situ doping process. To obtain good contact between TaN electrode and sensing material, reactive preclean was chosen instead of low-power Ar-preclean in order to control the sensing material loss. TaN was etched by standard Cu BEOL tool using CF4/CHF3 gas. The sensing material loss can be well controlled to less than 30nm, and the uniformity of sensing resistor was about 2sigma/mean >; 3% for 200A TaN. The TCR of the sensing resistor was about -1.5% ~ -2% which is compatible to the as-deposited sensing material film, and can well match this sensor application.
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关键词
tantalum compounds,semiconductor doping,cmos integrated circuits,modified cmos-beol process,integrated circuit interconnections,plasma cvd coatings,copper,boron,in situ doping process,cmos compatible mems process,microsensors,sacrificial material,optimized planarization process,cmos-mems interface structure,post interconnect single chip integration application,microbridge structure,pad layer,silicon,tan,detector circuits,alpha-silicon film,elemental semiconductors,cu,pecvd technology,si:b,sensor product application,electrode material,functional layer,copper beol line,cmos interconnect structure,cmos circuit,process control,chip,sensors
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