An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB
Anti-Counterfeiting, Security and Identification（2011）
摘要
An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5μm CMOS process and the active core area is 0.5*1.0 mm2. Measurement results show the A/D achieves 49.8dB peak SNDR and 68.7dB SFDR. The effect number of bits (ENOB) is 7.98. When the frequency of input signal is up to 5.477MHz, the A/D can also achieve more than 7 ENOB. The total power dissipates is 2.5-mW.
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关键词
cmos analogue integrated circuits,cmos process,sar a/d,frequency 1 mhz,power 2.5 mw,word length 8 bit,a/d,analogue-digital conversion,digital control block,sndr,successive approximation register,bootstrapped switch,charge redistribution,effect number of bits,size 0.5 mum,sfdr,enob,undersampling,adc,dynamic comparator,comparators (circuits),input signal,charge redistribution dac,sampling bootstrapped switches,bootstrap circuits,effective number of bits,registers,digital control,capacitors
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