3-D numerical simulation study on 20 nm NMOSFET design

The design requirement of the nano-scale bulk N-MOSFET with 20 nm effective gate length is studied in this paper based on the 3-D numerical simulation. To acquire the shallow source/drain extension profile, the PCl 5 implantation with low energy and rapid thermal anneals is performed. The halo implant is used to suppress the sub-threshold leakage and short channel effect. The final drives current of 320 A/um corresponding to the leakage current of 200 nA/um has been achieved in 20 nm N-MOSFET at V dd = 0.8 V. Copyright © 2011 American Scientific Publishers.