A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

This paper presents a VLSI architecture of CABAC decoder for H.264/AVC level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying context pre-fetch register set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13¿m technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.