Full custom design of a three-stage amplifier with 5500MHz·pf/mw performance in 0.18μm CMOS

2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC(2007)

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摘要
A full custom design of a three-stage amplifier is described in this paper. A feedback transconductance stage and a feedforward stage combined with two Miller compensation capacitors are used for frequency compensation. The circuit is designed in 0.18μm CMOS process with a 1.8V supply voltage. When driving a 150pF capacitive load, the amplifier achieves over 100dB dc gain, 2.24MHz gain-bandwidth product (GBW), 62° phase margin (PM), 1.2V/μs slew rate (SR) and 61μW power dissipation. Compared to conventional multistage amplifiers, this work provides improvement in both GBW and SR, and also shows a significant improvement in MHz·pF/mW performance.
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