Minimal area design of single pad power/ground tree

This paper deals with segment width optimization of single pad power/ground tree after the tree has been constructed. Given a routing topology of power or ground, our goal is to minimize the routing area of them under the constraints of maximum allowable voltage drops for maintaining proper logic level and switching speed, minimal width imposed by specific technology and metal migration. A procedure which uses Lagrangian Multiplier Algorithm is presented to minimize the area taken by power/ground routing with high running speed.