Timing-driven layout system for gate-array and standard-dell design-Tiger

Tiger is a fast timing-driven layout system for gate-array and standard-cell design. It can complete the whole layout process from placement to detailed routing and mask data generation. The timing issue is directly formulated and considered at every important stage of Tiger based on RC timing model. Several novel and efficient layout algorithms, such as the performance-driven placement algorithm-RITUAL, the performance-driven Steiner tree algorithms-IDW and CFD, the multi-terminal multi-commodity flow based timing-driven global routing algorithm, the vertical channel model based feed-through assignment algorithm-VERT and the global analysis based channel routing algorithm-DRAFT are used in Tiger. This may be the first complete timing-driven layout system ever reported. Experiments show that Tiger is much faster than Timber Wolf 6.0. It guarantees the chip performance while achieving comparable chip area with Timber Wolf.