Using LV Process to Design High Voltage DDDMOSFET and LDMOSFET with 3-D Profile Structure
International Symposium on Power Semiconductor Devices and IC's（2013）
Key words
CMOS integrated circuits,MOSFET,integrated circuit design,3D profile structure,DDDMOSFET,LDMOSFET,LV process,PW-NW junction,breakdown voltage enhancement,double diffused drain MOSFET,island patterns,lateral double diffused MOSFET,layout skills,slot patterns,standard low voltage CMOS technology,three dimensional fish bone patterns,voltage 10 V,voltage 5 V,voltage 60 V
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined