Dual-link interconnect architecture for 3-D Mesh-based network on chip

Network on chip (NoC), which is a new on chip communication infrastructure, is very sensitive to its area overhead, but has abundant wire resources. Furthermore, three dimensional (3-D) NoC designs provide short interconnection lengths between layers with interconnect scalability in the third dimension. This paper describes a dual-link interconnect architecture for 3-D mesh-based NoC designs. The design has dual links in the vertical direction to improve the communication bandwidth. Some of the vertical links cross through the intermediate layers to reduce the number of hops of messages in the third dimension. These both reduce the average latency and increase the maximal throughput with just a few additional control logic circuits. Simulations verify the theoretical analysis and show the performance advantages of this architecture with a relatively small increment of area overhead compared with the traditional one-link architecture.