Non-Inclusion Property in Multi-Level Caches Revisited

The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough micro- architectural techniques to move processor performance to higher levels, we are likely to see more and more on-chip cache memory in the years to come. Three levels of on-chip cache memory is not uncommon in recent designs. The increasing reliance on more on-chip cache requires more sophisticated cache design techniques and perhaps a rethinking of some cache concepts. We believe that a prime candidate for these concepts is the inclusion property. While simplifying memory coherence protocols in multiprocessor systems, this property makes inefficient use of cache memory real estate on the chip due to duplication of data on multiple levels of cache. Furthermore, strict enforcement of the inclusion property implies a "ripple effect" during updates where a single update in a cache level may result in several updates in the hierarchy above.