Hierarchical techniques for large-scale mixed-size placement

The problem of placement in VLSI CAD has been extensively studied for decades. However, it still draws active research attention as traditional flat approaches no longer work due to continual increase in design complexity and the shift in dominance of delay from modules to interconnects in deep sub-micron (DSM) technology regime. The hierarchical design approach is indispensable to handling the complexity of current and future designs. Moreover, ways to properly handle macro blocks of various sizes as well as standard cells are required, especially with the extensive reuse of IP blocks in SoC-style designs. In this dissertation, I propose a hierarchical method, based on min-cut partitioning and simulated annealing, to place very large SoC-style designs that may contain thousands of IP blocks of various sizes as well as millions of standard cells. To ensure the legality and better routability of the placed layout, an area budgeting technique is used during macro-aware partitioning. During simulated annealing, techniques to properly handle different bin sizes are required, because of the existence of large macro blocks. An efficient legalization algorithm is proposed to remove overlaps between modules and find the legal positions in the detailed placement stage. Moreover, a cell redistribution algorithm based on linear programming is proposed, which can be used to achieve desired cell distribution and improve the routability of the layout. Finally, experimental results are shown to validate the proposed algorithms.