An efficient approach for hierarchical submodule extraction

The growth of modern IC design complexity leads the consistency checks and design verification during every level in design flow to be an important and challenged issue. We propose an efficient approach to rebuild the hierarchial level from low level circuits. Our approach is based on the structure equivalent expansion algorithm to find repeated submodules in every circuit level to reconstruct circuit hierarchy. Without any additional library information, our approach is quite efficient in both time and space complexities by using only flatten netlists. The experiments on many real circuits containing combinatorial, sequential, and memory circuits show that our approach can rebuild most circuit hierarchial levels and also reduce the verification effort of the circuits.