A 7-bit 18th order 9.6 GS/s FIR filter for high data rate 60-GHz wireless communications

Jonathan Müller,Bruno Stefanelli,Antoine Frappe,Lu Ye,Andreia Cathelin,Ali M. Niknejad,Andreas Kaiser

ESSCIRC（2011）

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摘要

This paper presents the design and measurements of a 4× oversampled 18th order digital low-pass FIR filter aimed at replacing all analog baseband filters in a 60 GHz high data-rate wireless communication transmitter. Pipeline CPL adders and TSPC flip-flops are used to enable a very high output sample rate. The filter area is 0.1mm2 in a standard 65nm CMOS process. The interpolator has been designed to work at 10 GS/s. Measurements can be performed up-to 9.6 GHz on a 1.4V supply voltage and the filter consumes 400 mW.

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关键词

CMOS digital integrated circuits,FIR filters,adders,flip-flops,low-pass filters,radio transmitters,CMOS process,TSPC flip-flops,digital low-pass FIR filter,frequency 60 GHz,high data-rate wireless communication transmitter,pipeline CPL adders,power 400 mW,voltage 1.4 V

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