Transistor-Level Layout Of High-Density Regular Circuits
ISPD(2009)
摘要
In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate transistor-array-based layout. Interconnects on all metal layers are uni-directional and can be manufactured by an OPC-free process [4]. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.
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关键词
Regular fabric,Transistor layout,Placement and routing,DFM
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