Managing verification error traces with Bounded Model Debugging

ASP-DAC(2010)

引用 14|浏览21
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摘要
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior which drastically limits their application. This work presents bounded model debugging, an iterative, systematic and practical methodology to allow debuggers to tackle larger problems than previously possible. Based on the empirical observation that errors are excited in temporal proximity of the observed failures, we present a framework that improves performance by up to two orders of magnitude and solve 2.7x more problems than a conventional debugger.
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关键词
conventional debugger,bounded model debugging,empirical observation,key challenge,practical methodology,long verification error trace,logic arrays,iterative logic array,verification error traces,larger problem,automated debugging engine,model debugging,iterative methods,formal verification,observed failure,logic testing,image recognition,debugging,engines,logic gates,probabilistic logic,soc
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