The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3（2004）
Key words
full adder array,critical path,basic algorithm,basic circuit,new circuit,delay balancing,hardware synthesis,hash function,implementation option,pipelined version,ASIC Unit,Hash Function SHA-256,High Speed
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