A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
ISSCC（2009）
关键词
noise,delay locked loop,jitter,charge pump circuit,phase locked loops,delay lock loop,cmos,cmos integrated circuits,charge pump,gain,pll
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要