FPGA routing architecture: segmentation and buffering to optimize speed and density

    FPGA, pp. 59-68, 1999.

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    Abstract:

    In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distrib ution of routing segment lengths and the best mix of pass transistor and tri-state buffer routing switches. While most commercial FPGAs contain many length 1 wires (wires that span only one logic block) we find that wires this...More

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