Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
TRETS(2012)
摘要
Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.
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关键词
application-specific microarchitectures,reconfigurable computers,nonspeculative implementation,high overhead,actual data value prediction,memory latency,memory access,lightweight speculation,load value speculation,actual processor,nonspeculative part,memory system,speculative execution,fpga
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