BIST Algorithm for Embedded-DRAM Cores

The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called 1T- SRAM architecture). In this paper, we present our test algorithm for embedded-DRAM testing to test embedded DRAM's functionality and detect both SRAM and DRAM possible faults. The experimental results are collected based on 1-lot wafers with an 16Mb embedded DRAM core.