Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits

This paper introduces an efficient application intended for mapping under complex criteria applied to K -LUT based FPGA implemented circuits. This application is based on an algorithm that was developed taking into consideration a significant design factor - power consumption. Power consumption is considered in addition to other design factors that are traditionally used. To increase performance, it was used a flexible mapping tool based on exhaustive generation of all K -bounded sub-circuits rooted in each node of the circuit. Achieved information about logic dissipated power was obtained using an efficient dedicated simulator. In addition to lower power consumption, we devised several effective mapping techniques designed for reducing area and optimum depth.